Global bit lines are known as input/output (IO) or data lines in dynamic random access memories (DRAMs). Global bit lines are commonly built as differential pairs (i.e., lines GBL and corresponding lines GBLb), and serve to bi-directionally transfer the data between multiple memory banks and IO interfaces. For example, global bit lines transfer the read data from the memory banks to the interfaces, and transfer the write data from the interfaces to the memory banks. Depending on the architecture of the memory, there can be up to a thousand pairs of global bit lines GBL and GBLb in a memory. Further, global bit lines are very long, e.g., over 1 millimeter (mm). The capacitance on a global bit line is around several hundreds femtofarads (fF). Because of the large number of global bit lines, global bit lines are normal designed to be narrow, and therefore, have high resistance, e.g., around 2 kΩ.
To achieve high memory density and to save die areas, global bit lines usually do not have any intermediate amplifiers to boost the signals carried by global bit lines when the signals are weak. At high speed, e.g., above 400 MHz, however, propagating write signal data through global bit lines is difficult. For example, the write data on global bit lines need to be available at the memory bank inputs before the local bit line sense amplifiers are activated. Further, the data on global bit lines are to be at a rail-to-rail swing at the local bit line sense amplifier inputs. Achieving such goals is difficult because global bit lines are long, and the RC delay on global bit lines is high. RC delay is a time delay based on the resistance and capacitance characteristic of an electrical line.
Like reference symbols in the various drawings indicate like elements.